The present disclosure relates generally to information handling systems (IHSs), and more particularly to IHS processor performance state optimization.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system (IHS). An IHS generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, IHSs may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in IHSs allow for IHSs to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, IHSs may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
IHSs are generally understood in the art to operate using a processor to process information. Current processor control algorithms have been found through experimentation when running bursty applications to give higher performance and lower power consumption when using minimum and maximum performance states and transitioning between the two. A processor may process information by running as fast as possible to get a piece of work done and then sleeping the system until the next piece of work arrives. Traditionally, processors begin running at a lowest performance state and let the voltage continue to slew to a voltage required by the intended performance state and then transition the operating frequency once this occurs. However, with a processor having many performance states, the processor spends a large amount of time at the lowest speed with much higher voltages than required for the given operating frequency. This results in a power penalty for the performance of the processor obtained at the low operating frequency.
Accordingly, it would be desirable to provide improved processor performance state optimization absent the deficiencies described above.